Silicon carbide (SiC) is a semiconductor material with a high hardness which has a greater band gap than that of silicon (Si), and is applied in various semiconductor devices such as power devices, environment resistant devices, high-temperature operating devices, and high-frequency devices. Among others, applications to power devices such as switching devices and rectifier devices are drawing attention. A power device in which SiC is used has an advantage of e.g. a greatly reduced power loss than that of an Si power device.
Among power devices in which SiC is used, representative switching devices are metal-insulator-semiconductor field effect transistor (hereinafter abbreviate as MISFETs) and metal-semiconductor field effect transistors (MISFET). In such switching devices, based on a voltage which is applied to the gate electrode, it is possible to switch between an ON state where a drain current of several A (ampere) or more flows and an OFF state where there is zero drain current. Moreover, with SiC, a high breakdown voltage of several hundred V or more can be realized in the OFF state.
A switching device structure using SiC is proposed in Patent Document 1, for example. Hereinafter, with reference to the drawings, the structure of a vertical MISFET which is proposed in this document will be described.
FIG. 10 is a cross-sectional view illustrating an exemplary vertical MISFET.
In an SiC layer 102 which is formed on an SiC substrate 101, a drift region 102a, p type body (well) regions 106, source regions 108, and contact regions 107 are formed. Between adjoining body regions 106 on the surface of the SiC layer 102, a channel layer 103 is formed. On the channel layer 103, a gate electrode 110 is provided via a gate insulating film 104. The gate electrode 110 is covered by an interlayer insulating film 111. Each source region 108 and each contact region 107 are electrically connected to a source electrode 109 which is provided on the SiC layer 102. Through a contact hole which is formed in the interlayer insulating film 111, the source electrode 109 is electrically connected to upper wiring 112 provided on the interlayer insulating film 111. On the other hand, a drain electrode 105 is formed on the rear face of the SiC substrate 101. In an SiC power MISFET as shown in FIG. 10, the drift resistance can be greatly decreased because the thickness of the SiC layer 102 is reduced.
A method of producing the SiC power MISFET shown in FIG. 10 is disclosed in Patent Document 2, for example. FIG. 11(a) to (e) are cross-sectional views showing the production steps disclosed in Patent Document 2. Note that an MISFET is typically composed of a multitude of unit cells which are arrayed on a substrate, each unit cell being defined by a body region. FIG. 11(a) to (e) show portions of adjoining unit cells among such unit cells.
First, as shown in FIG. 11(a), after forming an SiO2 layer 324 on an SiC layer 302 which is grown on a substrate (not shown), by using this as a mask, impurity ions are implanted into the SiC layer 302. As a result, a plurality of body regions 306 are formed in the SiC layer 302, such that any region of the SiC layer 302 where the body regions 306 were not formed becomes a drift region 302a. 
Next, as shown in FIG. 11(b), a side wall 325 which is in contact with a lateral wall of the SiO2 layer 324 and a resist layer 323 covering a portion of each body region 306 are formed. Specifically, an SiO2 film (not shown) is deposited on the substrate surface on which the SiO2 layer 324 has been formed, and this is etched back to obtain the side wall 325. Next, after forming a resist film (not shown) on the substrate surface, this is patterned to form the resist layer 323. In a portion of the body region 306 that is covered by the resist layer 323, a contact region is to be formed in a subsequent step.
Next, as shown in FIG. 11(c), by using the SiO2 layer 324, the side wall 325, and the resist layer 323 as masks, impurity implantation in the SiC layer 302 is performed, whereby the source regions 308 are obtained. A distance Lg between an end of a body region 306 and an end of a source region 308 on the surface of the SiC layer 302 defines a “gate length” of the MISFET. After the implantation, the SiO2 layer 324, the side wall 325, and the resist layer 323, which were used as the masks, are removed.
Next, as shown in FIG. 11(d), a resist film 326 covering the substrate surface is applied over the SiC layer 302. Thereafter, through a known exposure and development process, the resist film 326 is patterned, thereby forming an opening 326a in a portion of each body region 306 where a contact region is to be formed.
Next, as shown in FIG. 11(e), p type impurity ions are implanted into the SiC layer 302 by using the resist layer 326 as an implantation mask, whereby a contact region 307 is obtained inside each body region 306.